__proof of concept only__


The system uses a custom System-on-Chip (SoC) running in an FPGA. Some IPs are off-the-shelf components (eg. CPU, SDRAM controller) and other are custom (eg. framebuffer IP).
  • hardware
    • Terasic DE0 board [P1100049_800x600.JPG]
    • Altera Cyclone3 FPGA EP3C16F484 / x16 8MB SDRAM / x16 4MB NOR FLASH
    • LQ043T1DG01 4.3" TFT (480x272) w/ custom adapter and backlight driver [P1100038_800x600.JPG]
  • HDL
    • nios2 32-bit RISC processor (softcore)
    • custom memory mapped framebuffer IP / RGB565 / assisted buffer swap [verilog]
    • UART / Timers / PWM (custom IP)
  • software
mm_fb_diagram_010711.pdf [memory mapped framebuffer IP block diagram]

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[02/2012] Copyright (c) 2010-2012 Noel Lemouel
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